Next Multi-core Architecture Cluster Meeting: April 7 (9-10:30), 2011 in Chamonix.
This cluster meeting will offer four interesting highlights of ongoing/just concluded multicore architecture projects:
- Energy-conscious 3D Server-on-chip for Green Computing (Eurocloud). Yanos Sazeides, University of Cyprus, Cyprus
- PARallel PAradigms and Run-time MAnagement techniques for Many-core Architectures (2PARMA). Cristina Silvano, Polytechnic University of Milano, Italy.
- An Integrated Approach to Transactional Memory on Multi and Many-core Computers (VELOX). Osman Unsal, Barcelona Supercomputing Center, Spain.
- Embedded Reconfigurable Architecture (ERA). Bilha Mendelson, IBM Research, Israel
Multi-core Architecture Cluster Meeting: October 19, 2010 in Barcelona.
This cluster meeting offered three interesting presentations:
- A Keynote presentation titled "Heterogeneous computers are the solution” -- What is the problem? by Avi Mendelson of Microsoft, Israel
- Overview of the TERAFLUX FP7 project by Roberto Giorgi, University of Siena, Italy.
- Overview of the ENCORE FP7 project by Alex Ramirez, Barcelona Supercomputing Center, Spain.
Research challenge:
The shift towards multi-core architectures poses several challenges for computer architects. With each new technology generation, there will be a significant increase of the number of transistors. The question is how computer architects can establish computational structures that can transform the increase in transistors into an equal increase in computational performance efficiency. This challenge must be attacked from several fronts, namely, the basic architecture of each processor (core) to increase single thread performance, via the architecture of the memory system, to a holistic approach to support emerging programming models that aim at reducing the efforts the programmers have to invest in designing software amenable to multi-core architectures. As a consequence, this cluster will be engaged in advancing state-of-the-art in the following areas:
Research topics:
- Processor architecture
- Memory hierarchy
- Technology impact on architecture
- Application impact on architecture
- Architecture support for parallel programming models
- Power/performance evaluation methodologies
Research issues:
- Scalability. How to provide an increase in computational performance that scales with the number of processor cores.
- Power. How to scale up the computational performance within the power budget.
- Reliability. How to scale up the computational performance taking into account reliability issues of future process technologies.
- Verification. How to increase computational performance in a complexity-effective way to keep verification efforts manageable.
- Parallel programmability. How to reduce the programming effort for multi-core architectures.
- Latency and bandwidth. How to keep the memory system latency manageable and how to scale up the memory system bandwidth in proportion to the increase in computational performance.
- Heterogeneity. How to best deal with heterogeneous architectures as a key approach to keep power within the envelope of the available technology.
- Resource management. How to utilize and manage computational resources in future multicore systems.
Major activities during 2009:
Three cluster meetings were arranged:- In connection to the 2009 HiPEAC conference in Paphos, Cyprus, on January 30.
- During the HiPEAC Computing Systems Week in Munich, Germany, on June 3.
- During the HiPEAC Computing System in Wroclaw, Poland, on October 28.
The theme of the first cluster meeting was to discuss and get agreement on the general issues according to Section 2.2.1. that are central to the research agenda of the cluster. The participants were divided into smaller groups of around 5-10 participants based on their interest to discuss e.g. power impact on processor archirtecture research. Very creative discussions took place that gave the participants added value.
The theme of the second cluster meeting was to debate the HiPEAC Roadmap document and especially how it aligns to the research in multicore architecture. The discussions that were spawned in this plenary session resulted in a revision of the document that better aligned not only with this cluster’s activities but also the activities in other architecture related clusters such as the one on Interconnects.
The third cluster meetings was run in a workshop like fashion. Apart from technical presentations of ongoing work some of the recently approved projects in the last call on Computing Systems were briefly introduced. The program was very full featuring four research presentations and brief introductions of the ENCORE and ERA FP7 projects.
In a collaboration with the Programming Models and Operating Systems cluster, the third MULTIPROG workshop will be arranged in Pisa as a satellite event to the 5th International Conference on High-Performance and Embedded Architectures and Compilers.
Major activities during 2008:
The activities during 2008 have aimed at compiling what research activities members of the cluster are involved in to set the direction for the future research activities on multicore architecture and stimulating it by organizing workshops.
Three cluster meetings have been arranged during the 2008:
- "Inaugaral" meeting in Goteborg in January, 2008 in conjunction with the HiPEAC conference
- A research workshop and roadmap meeting during the HiPEAC Computing Systems Week in Barcelona in June 2008
- A cluster meeting during the HiPEAC Computing Systems Week in Paris in November 2008
Apart from the “inaugural” meeting in Goteborg on January 27, 2008, which attracted close to a hundred attendees, the second meeting was held in Barcelona during the HiPEAC Computing Systems week. The purpose of that meeting was twofold. A first purpose was to give all members of the cluster a chance to present what they are doing by giving a 5-minute presentation. As many as 18 presentations were given spanning the following topics: processor/memory system architecture, locality management, power/performance issues, application impact on architecture. So indeed, the presentations matched the set of initial topics for the multicore architecture cluster quite well. The second purpose of the cluster meeting was to have a roundtable discussion on the roadmap. Based on Dr. Duranton’s questionnaire sent out to each cluster leader, a discussion took place that distilled the major challenges facing the multicore architecture area.
A task force to prepare the roadmap for the multicore architecture cluster was put together with the following individuals as members: Andre Seznec (INRIA), Sami.Yehia (Thales) Emre Ozer (ARM) , Yiannakis Sazeides (Univ. of Cyprus), Stefanos Kaxiras (Univ. of Patras), Alex Ramirez (Barcelona Supercomputing Center/UPC). This group distilled the first set of challenges for the roadmap which are summarized below:
- The Scalability, Power, Reliability, and Verification Challenge
- The Parallel Programming Challenge
- The Memory System Challenge
- The Heterogeneity Challenge
- The Resource Management and Instrumentation Challenge
The third cluster meeting was organized in the HiPEAC Computing Systems Week in Paris on November 27 2008. The main theme of this meeting was to present the new FP7 Call on Computing Systems that had been announced a couple of days before. Some important take aways from the call are that parallelization and reliability issues are stressed is relevant for many researchers in the cluster. It is however important that a successful consortium addresses all aspects from the application down to the architecture which is why successful consortia should be formed by groups from different HiPEAC clusters. It was encouraged that work on forming strong consortia should be initiated immediately.
To foster interaction between the multicore architecture and the programming model communities, three international workshops have been organized by the cluster leaders of the multicore architecture cluster (Per Stenstrom, Chalmers) and the programming model and operating system cluster (Osman Unsal and Eduard Ayguade of Barcelona Supercomputing Center). The first one, MULTIPROG 2008 took place at the 3rd International Conference on High-Performance and Embedded Architectures and Compilers in Göteborg on January 27, 2008. It attracted close to a hundred attendees and featured a keynote by Jesus Labarta as well as a set of technical sessions spanning topics across both clusters. A second international workshop – the Barcelona Multicore Workshop (BMW’08) – was arranged in Barcelona during the HiPEAC Computing Systems week with more than a hundred attendees. This workshop featured inspiring invited talks by international leaders in the community including leaders of the newly established centers at Stanford, Berkeley, and Illinois. Also, a panel with the theme “50 Billion Transistor Chips: What should the Hardware provide?" moderated by Yale Patt and “What Terrifies You More: Multicore Hardware or Software?" by Daniel Reed were arranged. Finally, based on the success of the first MULTIPROG workshop, a second edition took place at the 4th HiPEAC Conference in Paphos, Cyprus on January 25, 2009. Apart from technical sessions spanning architecture as well as programming model issues, it also featured an invited talk on the FET SARC project as well as a panel on multicore programming issues moderated by Per Stenstrom, Chalmers.
Planned activities:
- Programming Models and Operating Systems
- Reconfigurable Computing
- Interconnects
- Simulation Platform
Apart from stimulating ongoing research activities and align them well with the research direction set out by the roadmap activities across HiPEAC, the next set of activities will aim at foster cross-cluster activities. The multi-core research cluster has clear links to many of the other clusters but in particular to the following clusters: