HiPEAC 2012 - Paper track
Each presentation takes 25' plus 5' for questions.
| Session Id | Monday | Session Ttitle |
| Session Chair: Ben Juurlink | ||
| A | DAPSCO: Distance-Aware Partially Shared Cache Organization | Caches |
| Authors: Antonio García-Guirado; Ricardo Fernández-Pascual; Alberto Ros; Jose Manuel García (Spain) | ||
| A | Writeback-aware Partitioning and Replacement in Last-Level Cache of Phase Change Main Memory System | Caches |
| Authors: Miao Zhou; Yu Du; Bruce Childers; Rami Melhem; Daniel Mosse (United States) | ||
| Parallel Session I | ||
| Session Chair: Lasse Natvig | ||
| M | Sabrewing: a Lightweight Architecture for Combined Floating-Point and Integer Arithmetic | Micro Architecture |
| Authors: Tom Bruintjes; Karel Walters; Sabih Gerez; Bert Molenkamp; Gerard Smit (Netherlands) | ||
| M | SYRANT: SYmmetric Resource Allocation on Not-taken and Taken Paths | Micro Architecture |
| Authors: Nathanaël Prémillieu; Andre Seznec (France) | ||
| Break | ||
| Session Chair: Avi Mendelson | ||
| B | Hardware Transactional Memory with Software-Defined Conflicts | Transactional Memory |
| Authors: Ruben Titos-Gil; Manuel E Acacio; Jose Manuel García; Tim Harris; Adrian Cristal; Osman Unsal; Ibrahim Hur; Mateo Valero (Spain) | ||
| B | A Transactional Memory with Automatic Performance Tuning | Transactional Memory |
| Authors: Qingping Wang; Sameer Kulkarni; John Cavazos; Michael Fuchs Spear (United States) | ||
| B | FlexSig: Implementing Flexible Hardware Signatures | Transactional Memory |
| Authors: Lois Orosa Nogueira; Elisardo Antelo; Javier D. Bruguera (Spain) | ||
| Parallel Session II | ||
| Session Chair: Wolfgang Karl | ||
| N | sFtree: A fully connected and deadlock free switch-to-switch routing algorithm for fat-trees | Parallel Architectures |
| Authors: Bartosz Grzegorz Bogdanski; Sven-Arne Reinemo; Frank Olaf Sem-Jacobsen (Norway) | ||
| N | Bahurupi: A Polymorphic Heterogeneous Multi-Core Architecture | Parallel Architectures |
| Authors: Mihai Pricopi; Tulika Mitra (Singapore) | ||
| Lunch | ||
| Session Chair: Andre Seznec | ||
| C | ABS: A low-cost adaptive controller for prefetching in a banked shared LLC | Cache and Memory Techniques |
| Authors: Jorge Albericio; Rubén Gran; Pablo Ibáñez; Victor Viñals; Jose M. Llabería (Spain) | ||
| C | The Migration Prefetcher: Anticipating Data Promotion in Dynamic NUCA Caches | Cache and Memory Techniques |
| Authors: Javier Lira; Timothy M. Jones; Carlos Molina; Antonio Gonzalez (United States) | ||
| C | The Gradient-Based Partitioning Algorithm | Cache and Memory Techniques |
| Authors: William Hasenplaugh; Joel Emer; Aamer Jaleel; Pritpal Ahuja; Simon Steely (United States) | ||
| Break | ||
| Session Chair: Manolis Katevenis | ||
| D | Efficiently Exploiting Memory Level Parallelism on Asymmetric Multicore Processors | Multi-Core and GPGPUs |
| Authors: George Patsilaras; Niket Choudhary; James Tuck (United States) | ||
| D | Optimizing Explicit Data Transfers for Data Parallel Applications on the Cell Architecture | Multi-Core and GPGPUs |
| Authors: Selma Saidi; Pranav Tendulkar; Thierry Lepley; Oded Maler (France) | ||
| D | Exploring the Limits of GPGPU Scheduling In Control Flow Bound Applications | Multi-Core and GPGPUs |
| Authors: Roman Malits; Avinoam Kolodny; Avi Mendelson; Evgeny Bolotin (Israel) | ||
| Session Id | Tuesday | Session Ttitle |
| Session Chair: Koen Bertels | ||
| E | Using Machine Learning to Improve Automatic Vectorization | Loop Transformations |
| Authors: Kevin Stock; Louis-Noel Pouchet; P. Sadayappan (United States) | ||
| E | Polyhedral Parallelization of Binary Code | Loop Transformations |
| Authors: Benoit Pradelle; Alain Ketterlin; Philippe Clauss (France) | ||
| Break | ||
| Session Chair: Lieven Eeckhout | ||
| F | Compiler Techniques to Improve Dynamic Branch Prediction for Indirect Jump and Call Instructions | Back-End Compilation |
| Authors: Jason McCandless (Ireland) | ||
| F | Efficient Liveness Computation Using Merge Sets and DJ Graphs | Back-End Compilation |
| Authors: Dibyendu Das; Benoit Dupont de Dinechin; Ramakrishna Upadrasta (India) | ||
| F | Approximate Clustering of Program Graphs and its Application to Compilers | Back-End Compilation |
| Authors: John Demme; Simha Sethumadhavan (United States) | ||
| Lunch | ||
| Session Chair: Alex Ramirez | ||
| G | Toward High Throughput Algorithms on Many Core Architectures | Runtime Systems |
| Authors: Daniel Alberto Orozco; Elkin Eduardo Garcia; Rishi Khan; Kelly Livingston; Guang Gao (United States) | ||
| G | Seamlessly Portable Applications: Managing the Diversity of Modern Heterogeneous Systems | Runtime Systems |
| Authors: Mario Kicherer; Fabian Nowak; Rainer Buchty; Wolfgang Karl (Germany) | ||
| G | Thread Tranquilizer: Dynamically Reducing Performance Variation | Runtime Systems |
| Authors: Kishore Kumar Pusukuri; Rajiv Gupta; Laxmi Bhuyan (United States) | ||
| Break | ||
| Session Chair: Yiannakis Sazeides | ||
| H | An Architecture-Independent Instruction Shuffler to Protect against Side-Channel Attacks | Security |
| Authors: Ali Galip Bayrak; Nikola Velickovic; Paolo Ienne; Wayne Burleson (Switzerland) | ||
| H | Non-Monopolizable Caches: Low-Complexity Mitigation of Cache Side Channel Attacks | Security |
| Authors: Leonid Domnister; Aamer Jaleel; Jason Loew; Dmtry Ponomarev; Nael Abu-Ghazaleh (United States) | ||
| H | Compiler Mitigations for Time Attacks on Modern x86 Processors | Security |
| Authors: Jeroen Van Cleemput; Bart Coppens; Bjorn De Sutter (Belgium) | ||
| Session Id | Wednesday | Session Ttitle |
| Session Chair: Cristina Silvano | ||
| I | VSim: Simulating Multi-Server Setups at Near Native Hardware Speed | Architecture Simulation |
| Authors: Frederick Ryckbosch; Stijn Polfliet; Lieven Eeckhout (Belgium) | ||
| I | On the Simulation of Large-scale Architectures Using Multiple Application Abstraction Levels | Architecture Simulation |
| Authors: Alejandro Rico; Felipe Cabarcas; Carlos Villavieja; Milan Pavlovic; Augusto Vega; Yoav Etsion; Alex Ramirez; Mateo Valero (Spain) | ||
| Break | ||
| Session Chair: Stefanos Kaxiras | ||
| J | PLDS: Partitioning Linked Data Structures for Parallelism | Data and I/O Management |
| Authors: Min Feng; Changhui Lin; Rajiv Gupta (United States) | ||
| J | Dynamic Structure Layout Optimizations for Heap Objects | Data and I/O Management |
| Authors: Zhenjiang Wang; Chenggang Wu; Pen-Chung Yew (China) | ||
| J | ReNIC: Architecture Extension to SR-IOV Network for Efficient High Availability Replication | Data and I/O Management |
| Authors: Yaozu Dong; Yu Chen; Zhenhao Pan; Jinquan Dai; Yunhong Jiang (China) | ||
| Lunch | ||
| Session Chair: Sascha Uhrig | ||
| K | Multithreaded COTS Processors for Time-Critical Environments | Real-Time and Energy |
| Authors: Petar Radojkovic; Sylvain Girbal; Arnaud Grasset; Eduardo Quiñones; Francisco Cazorla; Sami Yehia (Spain) | ||
| K | TL-Fluid-Based Multi-Core Energy-Efficient Scheduling for Sporadic Real-Time Tasks | Real-Time and Energy |
| Authors: Dong Song Zhang; Deke Guo; Fangyuan Chen; Tong Wu; ShiYao Jin (China) | ||
| K | Utilizing RF-I and Intelligent Scheduling for Better Throughput/Watt in a Mobile GPU Memory System | Real-Time and Energy |
| Authors: Kanit Therdsteerasukdi; Gyungsu Byun; Jason Cong; Frank Chang; Glenn Reinman (United States) | ||
| Break | ||
| Session Chair: Bilha Mendelson | ||
| L | Toward an Accelerator-Based Architecture | Accelerator Architectures |
| Authors: Michael John Lyons; Mark Hempstead; Gu-Yeon Wei; David Brooks (United States) | ||
| L | Improving Performance of Nested Loops on Reconfigurable Array Processors | Accelerator Architectures |
| Authors: Yongjoo Kim; Jongeun Lee; Toan Mai Xuan; Yunheung Paek (Korea, Republic of) | ||
| L | Making wide-issue VLIW Processors Viable on FPGAs | Accelerator Architectures |
| Authors: Madhura Purnaprajna; Paolo Ienne (Switzerland) | ||
