Design and Simulation

Research challenge:

Electronic design automation (EDA) methodology and tools, especially its constituent simulation technologies, are key enablers for many HiPEAC research activities, such as multi-core and NoC architectures, or reconfigurable systems. In the light of moving towards 45nm and beyond CMOS technologies, and thus the urgent need for higher design productivity, EDA is currently aiming at a new abstraction level: Electronic System Level (ESL). ESL focuses on system design aspects 'beyond RTL', e.g. efficient HW/SW modelling and partitioning, efficient system simulation, mapping applications to MPSoC architectures, ASIP design, etc. These and other research topics are being addressed in the 'Design and Simulation' cluster. While ESL is currently mostly driven by the embedded system design community, due to the need to design efficient application specific systems with very limited resources (and thus with a higher acceptance of automation and tools), it can strongly benefit from many recent developments in the high-performance community (such as efficient compilation, programming models etc.), and vice versa. Therefore, another important goal of this cluster is to establish a closer link between different communities. Besides the regular cluster meetings, this is being implemented e.g. by coupling of existing platforms and tools, so as to achieve new heights in design productivity.

Scientific issues:

• Design methodology, tools and simulations driven by the trend towards multiprocessor system-on-chip (MPSoC) architectures.
• Applications include: wireless communications, multimedia, automotive.
• Very high efficiency goals (MIPS/Watt or Joule/bit), therefore programmable, yet application-specific and heterogeneous MPSoCs.
• Current shift towards Electronic System Level (ESL) design methodologies will provide the required next productivity boost beyond RTL design.
• Need for managing the complexity of today's and future digital chip designs in advanced CMOS technologies (45nm, 32nm, and beyond).

Research topics:

• Embedded processor design: ASIP design, design space exploration, configurable and reconfigurable processors, SW tools generation, retargetable compilation, processor/compiler co-design, loop parallelization, template based ASIP design, instruction set extensions, ultra-low power ASIPs, open source processor cores .
• Simulation platforms: increacing speed and accuracy (as modern embedded achitectures have high complexity), interoperability in form of standard interfaces for different tools.
• MPSoC modelling and verification: modelling languages, SystemC based modelling, verification and design, high-speed instruction set simulation, virtual platforms, path from model to implementation, NoC simulation.
• MPSoC programming: application-to-architecture mapping, parallel programming models, RTOS, task graph scheduling, sequential-to-parallel code generation, benchmarking.
• MPSoC HW/SW architectures: SW performance estimation, HW/SW integration, tightly coupled processor architectures, memory hierarchy, HW/SW interface synthesis, fault tolerance, loop transformations.

Major cluster activities in year 2011:

• RAPIDO workshop is organized annually with the main focus on rapid simulations and performance evaluation.
• RWTH Aachen - TU Tampere seminar: a joint seminar on tools and architectures was held in Tampere in May 2011.
• DATE special session: a special session on Virtual Platforms with invited speakers was organized at DATE 2011.
• HiPEAC booth at DATE 2011: were organized at one of the major events for design automation. New contacts have been established, and new members have been acquired.
• HiPEAC E.C. Technology Transfer: A workshop for horizon 2020 was organized in Brussels in April 2011.
• MAPS User Group Workshop (MUG): The first MUG was organized at the RWTH Aachen in September 2011.
• Joint master theses: e.g. a joint Master project on Source-to-Source code transformations is being performed by RWTH Aachen University and ALaRI, Lugano.

Coordinating partner: RWTH Aachen University & INRIA

Contact: Rainer Leupers, Olivier Temam