HiPEAC partners

The HiPEAC consortium consists of the following 14 partners:

Ghent University

Ghent University was founded in 1817. Today, after decades of uninterrupted growth, Ghent University is one of the leading institutions of higher education and research in the Low Countries. Ghent University offers high-quality, research-based education in all academic disciplines. Today Ghent University attracts over 30,000 students, with a foreign student population of over 1,100 EU citizens and some 1,000 students from non-EU countries. Excluding the Ghent University Hospital, the university employs 6800 staff members, including 912 professors. Its research budget for 2009 was 213 M€.

The Computer Systems Lab (CSL) of UGent's engineering faculty will participate in this project. The Lab (49 researchers, including 8 faculty members) is part of the Electronics and Information Systems Department. The part of the lab involved in this project conducts research on the hardware-software interface of programmable computing systems. This research spans the domains of system software, including compilers and operating and run-time systems, as well as computer architecture and micro-architecture component design. CSL has internationally recognized expertise in performance analysis, evaluation and modeling of modern multicore processors, fast simulation techniques, virtual machine designs, software protection techniques, reliability-enhancing software/hardware co-design, compiler techniques, and software parallelization techniques. CSL has active collaborations with leading American research groups at the University of Texas at Austin, the University of Wisconsin-Madison, the University of Arizona, the University of California, San Diego, IBM T.J. Watson, … It is also a partner in the recently started Intel Exascience Lab Flanders.

Staff member

 Koen De Bosschere is professor at the Engineering Faculty of Ghent University where he carries out research and teaches on computer architecture and operating systems. He is the head of CSL. He is author of 120 publications over the last 10 years. He is member of the computer science advisory board of the Fund for Scientific Research Belgium. He co-founded the HiPEAC1 Network of Excellence and he is the coordinator of the HiPEAC2 network of excellence, he is responsible for the ACACES summer school, and he has been instrumental in the development of the HiPEAC research vision.

Project management capabilities

Koen De Bosschere currently successfully manages the HiPEAC2 network of excellence. Ghent University has a long track record in high quality project management. Hundreds of projects have been successfully managed by the Ghent University Department of Research Affairs (with companies, local government, European Commission). Ghent University has a professional research coordination office and a technology transfer office that deals with the contractual aspects of projects.

Tasks

WP5 management, Award program, Summer school, Web site, Steering committee meetings, Reimbursement service, Administrative staff, Technical staff

Barcelona Supercomputing Center

The Barcelona Supercomputing Center-Centro Nacional de Supercomputación (BSC-CNS), established in 2005, serves as the National Supercomputing Facility in Spain. The mission of the BSC-CNS is to research, develop and manage information technologies in order to facilitate scientific progress. The BSC-CNS not only strives to become a first-class research centre in supercomputing, but also in scientific fields that demand high performance computing resources such as the Life and Earth Sciences. Following this approach, the BSC-CNS has brought together a critical mass of top-notch researchers, high performance computing experts and cutting-edge supercomputing technologies in order to foster multidisciplinary scientific collaboration and innovation. In addition, the BSC-CNS is one of the PRACE tier-0 centres.

The Computer Sciences Department of the BSC-CNS will be mainly contributing to HiPEAC3, providing his long background and software technologies to enable an efficient use of high-performance computing infrastructures. The department proposes novel architectures for processors and memory hierarchies, proposes novel programming models and innovative implementation approaches for these models as well as tools for performance analysis and prediction. In addition, the department does research on resource management at various component levels (processor, memory, interconnect and storage) and for different execution environments, including supercomputing and virtualized data centres.

Staff member

Mateo Valero, http://personals.ac.upc.edu/mateo/, is a professor in the Computer Architecture Department at UPC, in Barcelona. His research interests focuses on high performance architectures. He has published approximately 500 papers, has served in the organization of more than 200 International Conferences and he has given more than 300 invited talks. He is the director of the Barcelona Supercomputing Centre, the National Centre of Supercomputing in Spain. He co-founded the HiPEAC Network of Excellence.

Dr. Valero has been honoured with several awards. Among them, the Eckert-Mauchly Award, Harry Goode Award , the “King Jaime I” in research and two National Awards on Informatics and on Engineering. He has been named Honorary Doctor by the University of Chalmers, by the University of Belgrade, by the Universities of Las Palmas de Gran Canaria and Zaragoza in Spain and by the University of Veracruz in Mexico.  "Hall of the Fame" member of the IST European Program (selected as one of the 25 most influents European researchers in IT during the period 1983-2008 in Lyon, November 2008) 

In December 1994, Professor Valero became a founding member of the Royal Spanish Academy of Engineering. In 2005 he was elected correspondent Academic of the Spanish Royal Academy of Science, in 2006  member of the Royal Spanish Academy of Doctors and in 2008 member of the Academia Europaea. He is a Fellow of the IEEE, Fellow of the ACM and an Intel Distinguished Research Fellow. In 1998 he won a “Favorite Son” Award of his home town, Alfamén (Zaragoza) and in 2006, his native town of Alfamén named their Public College after him.

Tasks

Academic membership management, Mini-sabbaticals, HiPEAC anniversary event

Chalmers University of Technology

Chalmers University of Technology (Chalmers) was founded in 1829 following a donation by William Chalmers. It is among the top technical universities in Sweden and has around 10,000 students. The Department of Computer Science and Engineering has about 70 faculty members and 50 PhD students. One of its divisions, the Division of Computer Engineering, has a research orientation towards Computer Architecture and VLSI Design among other areas and engages two professors, three associate professors, two post-docs, and ten PhD students. The High-Performance Computer Architecture Group at Chalmers is primarily concerned with how to design future computer systems aimed at the embedded as well as at the high-end computing market. A key focus is on design principles and methods for multi-threaded processor architectures, memory systems, and performance evaluation methodologies. The focus of the research over the last 10-15 years has been on design principles for exploiting coarse-grained or thread-level parallelism in multiprocessors - a topic of perhaps higher relevance than ever today now as multi-core microprocessors are the mainstream. The group has contributed with a hundred international publications on cache coherence schemes, latency-tolerance techniques in multiprocessors using pre-fetching and relaxed memory consistency models and techniques to implement thread-level speculation. It has also paid attention to design issues for embedded systems, e.g., architectural tradeoffs to meet hard real-time and energy-effective demands.

Staff member

Per Stenström is a professor of computer engineering at Chalmers University of Technology since 1995. His research interests are on design principles for high-performance computer systems with an emphasis on high-performance memory systems. He has authored or co-authored three textbooks and more than a hundred publications in international journals and conferences. He is regularly serving program committees and acting as editor for major conferences and journals in the computer architecture field: ISCA, HPCA, IEEE Trans. on Parallel and Distributed Processing Systems, Journal of Parallel and Distributed Computing and he is the founding Editor-in-Chief of Transactions on High-Performance Embedded Architectures and Compilers. He co-founded the HiPEAC Network of Excellence. He has acted as general and program chair for a large number of conferences including the ACM/IEEE Int. Symposium on Computer Architecture, the IEEE High-Performance Computer Architecture Symposium, and the IEEE Int. Parallel and Distributed Processing Symposium. He is a Fellow of the ACM and the IEEE and a member of Academia Europaea and the Royal Swedish Academy of Engineering Sciences.

Tasks:

WP4 visibility, Conference, Newsletter

The University of Edinburgh

The School of Informatics at the University of Edinburgh is widely recognized as a world class centre for Computer Science research. The recent 2008 Research Assessment Exercise (RAE) confirmed Edinburgh's position as the UK's leading centre for research in Computer Science contributing 10% of the UK's world-leading research.

The proposed research is to be carried out at the Institute for Computing Systems Architecture (ICSA). ICSA has a vibrant research community with over 30 PhD students and an extensive research record in several areas directly related to this project: automatic parallelizing compilation, machine-learning based compilation and low power compilation/architecture co-design.

Edinburgh recently coordinated the EU FP6 MilePost project. This highly successful project has developed a machine-learning enabled version of GCC. MilePost GCC which has produced extensive interest in the industry and academia even featuring in the wall street journal. Edinburgh through its leadership of the project, has produced cutting-edge research in machine-learning enabled compilation.

Staff member

Professor Michael O'Boyle is internationally known for his ground breaking working in iterative compilation. This technology is now available in mainstream compilers. He has since pioneered incorporating machine learning into compilation, automating the design and construction of optimizing technology which has led to the release of MilePost GCC, the world's first open-source machine learning compiler.

He is a founding member of the High Performance and Embedded Architectures and Compilation Network of Excellence (NoE), the only European NoE in the area. Since 2005, he has been the European leader in HiPEAC's compiler research and development activity. He has been awarded 2 fellowships and 5 international visiting positions including a professorship at Stanford and an UK EPSRC Advanced Research Fellowship. He has published over 75 papers in international journals and conferences. He was the first to integrate machine learning in to dynamic compilation, auto-parallelization, feature generation and adaptive hardware. His recent work on streaming parallelism won the best paper and presentation awards at PACT this year. He is one of only a handful of Europeans to have published in the premier conferences in computer architecture: MICRO and HPCA and one of an even smaller number to have published at the top compilation conferences PLDI, OOPSLA and CGO. He has been a member on more than 50 PCs for every international conferences in his area and is the first ever European Program Chair for ACM CGO (Code Generation and Optimization) 2011, the premier conference for adaptive compilation.

Tasks

WP2 Mobility program, Collaboration grants, General mobility support, Supporting European champions: a low power platform ecosystem

FORTH

The Foundation for Research and Technology - Hellas (FORTH) is the premier research center in Greece, internationally acknowledged for its excellence in basic and applied research, in developing applications and products, and in providing services. The Institute of Computer Science (ICS), one of the seven Institutes of FORTH, will be contributing to this project. FORTH-ICS has a 27-year history of internationally competitive R&D contributions across the fields of Information & Communication Technologies, as well as of academic and industrial cooperation; it has adopted an evolving strategy to promote the commercial exploitation of R&D results by providing services, licensing products to industrial partners, contracting with industrial partners to jointly develop new products, and participating in spin-off companies and joint ventures. FORTH-ICS represents Greece in the European Research Consortium for Informatics and Mathematics (ERCIM). The Institute ranked first among all Greek institutes of its field in both of the two national evaluation rounds so far.

Contributions to this project will come from the Computer Architecture and VLSI Systems (CARV) Laboratory of FORTH-ICS; it has a 24-year history in architecture, hardware, and systems software R&D, with fundamental contributions in interconnection network architectures, in cluster computing, and, more recently, in scalable systems, in runtime systems and parallel programming and applications, in storage and I/O subsystems, and in infrastructure services engineering. CARV expertise includes the design, implementation, and test of dozens of innovative FPGA, ASIC, board, and System Software prototypes.

In Interconnection Networks, FORTH-ICS worked in 1986-92 on fair queueing, backpressure, congestion tolerance, weighted round-robin scheduling, and multiprocessor interconnects; in 1996-98, a 6-million-transistor switch chip was designed and built; recent contributions were in wormhole IP over ATM, weighted fair queueing, congestion elimination in switching fabrics, buffered crossbars, and high-radix crossbar networks-on-chip (NoC).

In Scalable Architectures, FORTH-ICS has an 18-year history: in the Telegraphos project (1993-95), workstation clustering prototypes were designed and built, including processor network interfaces for protected user-level communication. In the last 8 years, FORTH-ICS works on low-latency and high-bandwidth communication in chip multiprocessors, and in scalable parallel processing – at the layers of hardware architecture and runtime system, and their interactions. Contributions in the area of runtime systems are in dynamic extraction and scheduling of parallelism, locality management, synchronization protocols, scalable software-managed coherence, and integration with programming languages and models.

In Storage and I/O Architectures, FORTH-ICS has built two large scale working prototypes, currently used for further research: a scalable distributed storage prototype, with the full I/O stack in the system kernel developed in-house; and a 10-Gbit/s communication subsystem and SAN (storage area network) prototype, including the hardware platform and the full software stack. CARV currently coordinates the IOLanes and TransForm projects, and participates in the Stream, CumuloNimbo, Encore, Text, and Scalus projects.

Staff member

Professor Manolis Katevenis received his PhD degree in Computer Science from U.C. Berkeley in 1983, where he was the chief implementer of the RISC II single-chip microprocessor (precursor of the SUN SPARC architecture); for this work he received the 1984 ACM Doctoral Dissertation Award. In 1984-85 he was Assistant Professor at Stanford University, and since 1986 he is with the Univ. of Crete, where he is currently Professor, and with FORTH-ICS where he heads the CARV Laboratory; see http://www.ics.forth.gr/~kateveni. He co-founded the HiPEAC Network of Excellence.

Tasks

Computing systems weeks

INRIA

INRIA is the main French research institute dedicated to information technology. It networks skills from the fields of information, computer science and technology from the entire French research system. Throughout its six research units in Rocquencourt, Rennes, Sophia Antipolis, Lyon-Grenoble, Nancy and Bordeaux-Lille-Saclay, INRIA has a workforce of 3,500 employees, distributed across 120 joint research projects; in addition to its academic output, INRIA has led to the creation of more than 80 start-ups.

The INRIA groups involved in HiPEAC2 are Saclay (Alchemy), Rennes (ALF) and Lyon (CompSys). Most of the researchers involved in this project have a long history of collaborating together, several researchers having moved from one research unit to another, leading to cross-fertilization and merging of the different research topics and approaches.

The research in these INRIA groups covers a wide range of topics, from processor micro-architecture to compiler optimizations, programming paradigms and methodology issues. Our research groups have made significant contributions in memory and ILP improvement techniques. They are now targeting long-term multi-threaded/multi-core architectures from micro-architecture, reconfigurable architectures for customized accelerators, compilation and programming model perspectives together. INRIA is also working on the practical implementation issues of iterative optimization. In terms of methodology, it is working on thermal modeling for multi-cores, and has significant efforts on compiler and simulation platforms.

Staff member

Olivier Temam graduated from Ecole Centrale de Paris in 1990, and then he has obtained a PhD in Computer Science from University of Rennes in 1993. He has been Assistant Professor at University of Versailles from 1994 to 1999, and then Professor at University of Paris Sud until 2004. Since then, he has been a Senior Researcher at INRIA Futurs in Paris (Saclay), where he heads the Alchemy group. He is also an Adjunct Professor at Ecole Polytechnique where he teaches computer architecture. His research interests include processor architecture and simulation, program optimization, emerging technologies and their impact on long-term architecture and programming. He has been a visiting scientist at University of Illinois (US), University of Leiden (The Netherlands), UPC (Spain) and ICT (Beijing, China).

He is regularly publishing in, and part of the Program Committees of, top conferences such as MICRO, ISCA, ASPLOS, HPCA, CASES, etc. Since 2002, 9 PhDs have defended under his supervision, one of them scoring the award for best French PhD in Computer Science. Olivier Temam has also actively participated to the creation of the European HiPEAC1 Network of Excellence, and was a steering committee member of HiPEAC1 & 2, and he is now involved in several IST and FET projects.

Tasks

WP3 research coordination, Technology seminars, HiPEAC workgroups

RWTH Aachen University

 RWTH Aachen University, Germany, is an internationally top-ranked technical university with more than 30,000 students and is a member of the IDEA league. Its Institute for Communication Technologies and Embedded Systems (ICE), being part of the RWTH Department of Electrical and Computer Engineering, is headed by Prof. R. Leupers, Prof. G. Ascheid, and Prof. A. Chattopadhyay. ICE performs research and development in different areas of embedded system design technology, especially covering algorithms, architectures, and tools for wireless communication systems. ICE maintains tight cooperations with semiconductor vendors, system houses, and EDA companies, and frequently provides industrial consulting services. ICE receives funds from the Deutsche Forschungsgemeinsschaft (DFG), e.g. via the Excellence Cluster UMIC (Ultra High Speed Mobile Information and Communication), a large scale next-generation mobile internet research program. Further funding is received from EU projects like EURETILE, 2PARMA, HiPEAC, ARTIST, and NEWCOM, as well as from industry partners like Nokia, Ericsson, Synopsys, ACE, and Huawei Technologies. Many R&D projects at ICE have contributed to the development of industrial products. Moreover, several successful EDA spin-off companies originated from ICE, e.g. Cadis (acquired by Synopsys), Axys (acquired by ARM), and LISATek (acquired by CoWare, now with Synopsys).

Staff member

Rainer Leupers received the M.Sc. (Dipl.-Inform.) and Ph.D. (Dr. rer. nat.) degrees in Computer Science with honors from the Technical University of Dortmund, Germany, in 1992 and 1997. From 1997-2001 he was the chief engineer at the Embedded Systems chair at TU Dortmund. During 1999-2001 he was also a team leader at ICD, where he headed industrial service projects. In 2002, Dr. Leupers joined RWTH Aachen University as a professor for Software for Systems on Silicon. He is also a visiting faculty member at the ALARI institute in Lugano. His research and teaching activities comprise software development tools, processor architectures, and electronic design automation for embedded systems, with emphasis on multiprocessor system-on-chip design tools. He published numerous books and technical papers, and he served as a program committee member and topic chair of leading international conferences, including DAC, DATE, and ICCAD. He was a co-chair of the MPSoC Forum and SCOPES. Dr. Leupers received several scientific awards, including Best Paper Awards at DATE 2000, 2008 and DAC 2002. He has been a co-founder of LISATek, an EDA tool provider for embedded processor design, now part of Synopsys Inc. He has served as consultant for various companies, as an expert for the European Commission, and in the management boards of compound research projects like UMIC, HiPEAC, and ARTIST.

Tasks

WP1 membership program, Industrial membership management, Reaching out to new member states and beyond

ARM

ARM Ltd is a world renowned UK-based semiconductor IP company, whose most visible product is the ARM 32-bit RISC Processor family. This CPU family is the most widely used architecture in embedded systems. It is the architecture of choice for more than 80% of the high-performance embedded products in design today. When ARM pioneered the concept of openly licensable IP for the development of 32-bit RISC microprocessor-based SoCs in the early 1990s, it changed the dynamics of the semiconductor industry forever. By licensing, rather than manufacturing and selling its chip technology, the Company established a new business model that has redefined the way microprocessors are designed, produced and sold. More importantly, ARM has shaped a new era of next-generation electronics: ARM Powered microprocessors are pervasive in the electronic products we use, driving key functions in a variety of applications in diverse markets, including automotive, consumer entertainment, imaging, microcontrollers, networking, storage, medical, security, wireless, smartphones and most recently netbooks and servers. ARM licenses its IP (e.g. single and multi-core CPUs, AMBA coherent buses, cache, DMA and memory controllers) to a network of more than 200 Partners, which includes some of the world's leading semiconductor and system companies, including 19 out of the top 20 semiconductor vendors worldwide. These Partners utilize ARM's low-cost, power-efficient core designs to create and manufacture microprocessors, peripherals and SoC solutions. As the foundation of the company's global technology network, these Partners have played a pivotal role in the widespread adoption of the ARM architecture. To date, ARM Partners have shipped about 20 billion ARM microprocessor cores.

Staff member

Emre Ozer is an R&D Staff engineer at ARM since 2005. He received his Ph.D. in the Department of Electrical and Computer Engineering at North Carolina State University in 2001. He worked in Sun Microsystems, HP Labs, Motorola StarCore and Trinity College Dublin, occupying positions of research engineer, computer architect and research fellow. His research interests are energy-efficient computing, many-core architectures, multithreading, low-power servers, fault tolerance and reliability. He is the reviewer of several conferences and journals, has published over 20 conference and journal articles, and holds 3 US patents. He represents ARM in the steering and executive committees of the following EU projects: FP6 HiPEAC Network of Excellence, FP7 HiPEAC2 Network of Excellence and FP7 SARC Integrated Project. He is currently the coordinator of FP7 ICT Computing Systems project called EuroCloud.

Tasks

Internships

Commissariat à l'énergie atomique et aux énergies alternatives (CEA)

CEA is the French Atomic Energy Commission (Commissariat à l’Energie Atomique et aux Energies Alternatives, http://www.cea.fr). It is a public body established in October 1945. The CEA is active in three main fields: Energy, information and health technologies, and defense and national security. In each of these fields, the CEA maintains a cross-disciplinary culture of engineers and researchers, building on the synergies between fundamental and technological research. CEA has a workforce of around 15000 employees.

Within CEA Technological Research Division, institutes lead research in order to increase the industrial competitiveness through technological innovation and transfers:

The CEA-LIST, Laboratory of applied research on software-intensive technologies, which is based near Paris at Saclay and Fontenay-aux-Roses, is a key software systems and technology research center working in three areas with vital societal and economic implications:

• Embedded systems (architecture and design of systems, methods and facilities for software and system dependability, and intelligent vision systems);

• Interactive systems (knowledge engineering, robotics, virtual reality and sensorial interfaces);

• Signal detection and processing.

With the strong project-centered culture of its 450 researchers, engineers and technicians, the LIST is able to perform research work in partnership with the major industrial players in the nuclear, automotive, aeronautical, defense and medical fields and thus investigate and develop innovative solutions corresponding to their requirements.

The LIST, which is actively engaged in research work extending from conceptual design of systems to pre-industrial prototypes, contributes to the transfer of technology and encourages innovation, particularly by assisting the emergence of new businesses and startups.

LIST teams have worked as partners with numerous university laboratories, engineering schools and other research establishments on collaborative research projects.

The CEA LETI is the Laboratory of Electronics and Information Technology of CEA. Created in 1967 in Grenoble, LETI is one of the leading research institutes in Europe. Its mission is to develop innovative solutions which leads to industrial transfers or start-up creation and, meanwhile, to explore prospective fields in collaboration with academia. LETI’s activities cover Silicon technology, microsystem technology, optical components, multimedia, transmission and telecommunication systems, design, and micro technologies for health and biology.

The Design Architectures & Embedded Software Division (DACLE division), common to CEA-LETI and CEA-LIST, gathers more than 200 people focusing on digital and SoC, design for image, RF, design environment and embedded software. The Embedded Computing Laboratory (LCE), part of DACLE, provides expertise in advanced computing architecture for embedded applications and highly integrated system design, highly integrated / massively parallel processors, reconfigurable computing, computing systems for vision applications and computing architecture for future technologies.

In the HiPEAC3 Network of Excellence, CEA LCE will be in charge of the roadmap activity. With its collaboration with industries, startups and academia, together with its wide internal activities including future technologies silicon or non silicon based, CEA is ideally placed to collect trends and coordinate the activities related to future trends and roadmap in the domain of High Performance and Embedded Architecture and Compilers.

Staff member

Dr. Marc Duranton is a senior member of the Embedded Computing Lab, part of the CEA LIST DACLE. He previously spent more than 23 years in Philips, Philips Semiconductors and NXP Semiconductors. He has two MSc degrees, in electrical engineering and in computer science, from ENSERG and from ENSIMAG, both in Grenoble and a PhD in signal and image processing from Institut National Polytechnique de Grenoble.

He worked within Philips Semiconductors in California on several video coprocessors for the VLIW processor TriMedia and for various Nexperia platforms. In NXP Eindhoven (The Netherlands), he led the Ne-XVP project which targeted the design of the hardware and software of a multi-core processor for real-time video applications. He also led the architecture of a baseband for a millimeter wave transmission system and realized several digital processor using neural networks techniques. His research interests include parallel and high performance architectures for video and image processing including vision, domain specific architecture, system modeling and validation, models of computation for (hard) real-time systems, software optimization, compiler technology and emerging paradigms for computing systems. He has published several articles and book chapters, and more than 30 patents. He was in charge of the roadmap activity in the Network of Excellence HiPEAC2.

Tasks

Roadmap

Ericcson AB

Ericsson AB is a company in the Ericsson Group. The Ericsson Group is a world-leading provider of telecommunications equipment and related services to mobile and fixed network operators globally. Over 1,000 networks in more than 175 countries utilize our network equipment and 40 percent of all mobile calls are made through our systems. We are one of the few companies worldwide that can offer end-to-end solutions for all major mobile communication standards. Reflecting our ongoing commitment to technological leadership, we have one of the industry's most comprehensive intellectual property portfolios containing over 25,000 patents, number 1 in mobile telecom.

Ericsson AB, Sweden has extensive experience in software research and a long-standing experience in developing both large scale, massively parallel and embedded systems deployed worldwide as part of the most advanced telecommunication networks. Ericsson is the original designer and implementer of the open source languages Erlang and Feldspar, both high level domain specific languages successfully deployed in large scale and research projects. Ericsson AB has a long background in successfully leading and participating in international projects such as the EU-funded ACTORS, PROTEST, CHESS, PSIRP, 4WARD or SAIL projects, all involving industrial and academic partners from several countries

Staff member

András Vajda is driving the parallel computing and cloud computing research at Ericsson. He has over 10 years of experience in architecting and designing massively parallel and distributed software systems. His main research interests include scalability of operating systems and telecom software to massively multi-core systems as well as the design of software for cloud computing environments, actively participating in EU-funded projects. He is member of IEEE, ACM and serves on the steering group and advisory board of several research groups in the field, such as the Industrial Multicore Center at the Swedish Institute of Computer Science and the UPMARC research center at the University of Uppsala in Sweden.

Tasks

Dissemination of research results

IBM Israel Science and Technology Ltd

IBM Israel Science and Technology Ltd IBM has the world's largest IT research organization, with more than 3,000 scientists and engineers working at 8 labs in 6 countries. IBM invests more than $5 billion a year in R&D and is the world’s leader in patent filings.

In aggregate, the company holds nearly 37,000 patents worldwide. IBM Israel Science and Technology Limited is better known as IBM Research – Haifa. Since it first opened as the IBM Scientific Center in 1972, the Haifa lab has conducted decades of research that have proved vital to IBM’s success. The lab is one of five research laboratories located outside of the United States, and has close working relationships with IBM Israel and its twin research laboratory in Zurich. In Haifa, 25 percent of the technical staff has doctorate degrees in computer science, electrical engineering, mathematics, or related fields. Employees are actively involved in teaching in Israeli higher education institutions and in supervising post-graduate theses. R&D projects are being executed today in areas such as storage systems, cloud computing, healthcare and life sciences, verification technologies, business transformation, information retrieval, programming environments, optimization technologies, and analytics.

In code optimization technologies, HRL focuses on a range of optimization problems, both in compilers and post-link optimization tools which take advantage of the underlying structure of modern VLIW and superscalar processors (e.g. PowerPC). Haifa's researchers contributed to IBM's proprietary technology components as well as to open source tools such as the GNU C Compiler (GCC). In the context of GCC, IBM Haifa has been involved in researching sophisticated optimization techniques such as global and local instruction scheduling, modulo scheduling, auto-vectorization, auto-parallelism etc. Complementary to optimizing compilers, HRL developed post-link binary instrumentation and optimization technology, called FDPR-Pro. The FDPR-Pro tool uses the profiling information and the program global view to optimize the most frequently executed pieces of code, potentially at the expense of the rest of the program. This technology proved itself in a variety of market segments such as database engines, embedded software components, etc. The Haifa researchers started looking into new promising domains such as dynamic and adaptive monitoring and optimization of long running programs, architectures of media processors (e.g. DSPs) and related code optimization problems, exploitation of machine learning techniques for iterative optimization, etc.

Staff member

Dr. Bilha Mendelson has been a member of the Haifa Research Laboratory in Haifa for several years. She worked on avionic real-time systems at Elbit Ltd. before attending graduate school. In 1990 she joined the Haifa Research Laboratory. She has been developing compiler optimizations for compiler for DSP and also for the AS/400 optimizing translator. Currently she is a senior manager of the Code Optimization and Quality Technologies Department. As part of this role, she is leading projects that are mulit-site projects mainly in the areas of performance improvements, compiler optimizations, post-link optimizations and software quality. She participated in program committees of leading conferences, published several papers and holds patents in these areas. She received a B.Sc. and M.Sc. in computer science from the Technion - Israel Institute of Technology, Haifa, and Ph.D. in computer engineering from the University of Massachusetts at Amherst. Her areas of interest include code optimization algorithms, compiler technology, computer architecture, and performance improvement issues.

Tasks

Industrial workshops

Recore Systems

Recore Systems is a fabless semiconductor company that develops advanced digital signal processing platform chips and licenses reconfigurable semiconductor IP. Recore's technology enables ultra energy-efficient digital signal processing in products such as cell phones, digital radios/TVs and infotainment/navigation systems.

The company is specialized in reconfigurable multi-core designs that allow instant adaptation to new situations and offer a unique combination of flexibility, high performance, low power and low cost. Scalability of the technology allows use in both consumer and high-end applications.

Recore's reconfigurable technology comprises innovative processor cores, design tools for easy integration in customer solutions and ready-to-use applications. Besides reconfigurable hardware solutions, Recore provides accompanying IDE tools, software libraries and application engineering services.

Staff member

Paul Heysters has more than 7 years experience working in the field of reconfigurable computing. In his career, he has worked for high-technology companies in both Europe and the USA, including Ericsson, Philips and Chameleon Systems. Before co-founding Recore Systems, he led research on coarse-grained reconfigurable computing for the Chameleon project at the University of Twente (The Netherlands) and worked collaboratively with industry organizations.

Paul received his MSc degree in Computer Science from the University of Twente in 1998 and his doctorate in 2004 for his PhD thesis entitled “Coarse-Grained Reconfigurable Processors – Flexibility meets Efficiency.” Paul Heysters is co-founder of Recore Systems.

Tasks

Conference Travel

ST Microelectronics SRL, Italy

STMicroelectronics is the world’s fifth largest semiconductor company with net revenues of US$ 8.51 billion in 2009. According to the latest industry data from iSupply, ST-Italy holds market leadership in many fields. The Company is the leading producer of application-specific analogue chips and power conversion devices. It is the #1 supplier of semiconductors for the Industrial market, set-top box applications, and MEMS (micro-electromechanical systems) chips for portable and consumer devices, including game controllers and smart phones. ST-Italy also occupies leading positions in fields as varied as automotive integrated circuits (#3), chips for computer peripherals (#3), and the rapidly expanding market for MEMS overall (#5).

Product Portfolio

ST-Italy aims to be the leader in multimedia convergence and power applications, offering one of the world’s broadest product portfolios, including application-specific products containing a large proprietary IP content and multi-segment products that range from discrete devices to high-performance microcontrollers, secure smart card chips and MEMS devices. The Company provides solutions for a wide array of Digital Consumer applications, with a particular focus on set-top boxes, digital TVs and digital audio, including radio. In the Computer Peripherals arena, ST-Italy provides leading solutions in data storage, printing, visual display units, power management for PC motherboards, and power supplies. A wide range of ST-Italy’s ASSPs (Application Specific Standard Products) power sophisticated Automotive systems such as engine control, vehicle safety equipment, door modules, and in-car infotainment. The company also supplies industrial integrated circuits (IC) for factory automation systems, chips for lighting, battery chargers and power supplies, as well as chips for advanced Secure Access applications. ST-Italy pioneered and continues to refine the use of platform-based design methodologies for complex ICs in demanding applications such as mobile multimedia, set-top boxes and computer peripherals.

Research & Development and Manufacturing

Since its creation, ST-Italy has maintained an unwavering commitment to R&D and is one of the industry’s most innovative companies. In 2009, ST-Italy spent US$2.37B in R&D, which is approximately 28% of the Company’s 2009 revenues. ST-Italy’s process technology portfolio includes advanced CMOS (Complementary Metal Oxide Semiconductor) logic including embedded memory variants, mixed-signal, analogue and power processes. ST-Italy has a worldwide network of front-end (wafer fabrication) and back-end (assembly and test and packaging) plants. ST-Italy has established a worldwide network of strategic alliances, including product development with key customers, technology development with customers and other semiconductor manufacturers, and equipment- and CAD-development alliances with major suppliers.

Staff member

Dr. Giuseppe Desoli is a STMicroelectronics Fellow, with more than 15 years of experience in the field of computer architectures and Systems on Chips. He graduated in Electronics Engineering from the University of Genoa, Italy in 1991 (summa cum laude) where he also received a PhD in Telecommunications in 1995, working in the field of parallel architectures and algorithms for signal and image processing; he joined HP Labs at the Cambridge Lab in Massachusetts, USA from 1995 to 2002, doing research in VLIW architectures with a special focus on embedded custom defined microprocessors, tools and binary translation technologies, working together with some of the most influential pioneers of the field. He later came to STMicroelectronics, attracted by practical application of VLIW processors platforms to embedded devices and SoCs, and he has lead a microprocessors research group within the advanced system technology R&D group of ST-Italy. He’s in charge of various advanced SW and HW R&D projects also focused on Linux applied to multimedia SoCs. He's co-authored more than 50 scientific publications on both computer science and signal processing and he holds many patents with both the European and US patent offices and is an associate editor for the IEEE Trans on Industrial Informatics. Dr. Desoli has an extensive funded project management expertise having participated and managed a large number of EU funded project in FP6 and FP7 on behalf of STMicroelectronics.

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THALES SA

Thales operates in highly specialized fields such as air traffic management, avionics, secure military communications and large-scale information networks for governments and administrations. Designing and developing the mission-critical information systems that underpin the company’s leadership in aerospace, defense and security markets calls for comprehensive expertise in increasingly sophisticated technologies and the ability to integrate these technologies with large-scale software driven systems.

TRT comprises four research entities in France, the UK, the Netherlands and Singapore, as well as laboratories managed jointly by corporate research and Group subsidiaries and a network of research departments in operating units. TRT France, located since 2006 on the campus of the Ecole Polytechnique engineering school, employs 220 full-time staff, and some 40 doctoral students and 50 outside researchers are present on site at any one time.

TRT research comes under three main headings:

• Hardware systems and components research is mainly conducted by TRT France and includes microwave systems for land-based, naval and airborne radars and electronic warfare, optronics systems for detection and countermeasures, and security systems to protect people and property: identity cards, gas and explosive detection, biometrics, site security,

• Software technology research aims both to reduce risk and raise the productivity of software engineers working on software-intensive systems and embedded software, and to provide a technological edge in the systems Thales sells. Research is devoted to four areas: new technologies for system engineering and software with a high standardization component; software and middleware architectures; hardware and software environments for high-performance data and signal processing; and smart software systems for autonomous management, control and decision-making in critical situations,

• Software system research, mainly conducted in the UK, focuses on four major system functions: communications technology, positioning and navigation services (particularly for security systems), signal processing and data fusion, and virtual office technologies for collaborative working environments.

Staff member

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